SAR AD Converter papers (2011-2013)

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS
Erwin Janssen, Kostas Doris, Athon Zanikopoulos, Alessandro Murroni,
Gerard van der Weide, Yu Lin, Ludo Alvado, Frederic Darthenay, Yannick Fregeais
– IEEE International Solid-State Circuits Conference Digest of Technical Papers – 2013

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals
Yu Lin, Kostas Doris, Erwin Janssen, Athon Zanikopoulos, Alessandro Murroni,
Gerard van der Weide, Hans Hegt, Arthur van Roermund
– Proceedings of the ESSCIRC – 2013

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard van der Weide
– IEEE Journal of Solid-State Circuits – Year 2011, Volume 46, Issue 12

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist
Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide

– IEEE International Solid-State Circuits Conference – 2011

A direct sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS
E. Janssen, K. Doris, A. Zanikopoulos, G. van der Weide, M. Vertregt, O. Jamin, F. Courtois, N. Blard, M. Kristen, S. Bertrand, F. Riviere, F. Deforeit, G. Blanc, Y. Penning, F. Lefebvre,
D. Viguier, M. Dubois, V. Vrignaud, C. Cazettes, L. Schaller, G. Jenvrin
– Symposium on VLSI Circuits – Digest of Technical Papers – 2011